The present invention relates to a correcting method and a correcting system for a mask pattern which is applicable for all of wafer processes such as lithography and etching.
Semiconductor integrated circuits have become smaller and smaller, and critical dimensions (CD) of a pattern is on the order of a submicron. When such a finely divided pattern is subjected to, e.g., a lithography process, it is difficult to obtain a desired pattern shape due to an influence of an approaching pattern (hereinafter called "optical proximity effect"). When a semiconductor integrated circuit including a memory, a logic circuit and the like is produced, if a lithography process is conducted while setting a light exposure condition in a region of the memory cell which is designed in the minimum size, a light exposure condition of a peripheral circuit is deviated from the optimum value due to the optical proximity effect. As a result, a width of the produced pattern unintentionally becomes wider or narrower than a designed value. Thereupon, those related to the present filed are more and more interested in a optical proximity correction (OPC) method for correcting a mask pattern in accordance with a pattern which is deviated from the designed value. However, a strict or perfect OPC method has not yet been established.
There is a method using a simulation as one example of conventional OPC methods. This simulation is a method for simulating an actual circuit using, as a parameter, data concerning the lithography. In the case of this method, because data of CAD (Computer Aided Design) can be used, there is a merit that a mask pattern can be corrected by a simple process. However, since only data concerning the lithography can be used in the method, it is difficult to make an accurate correction. This is because the wafer process includes not only aerial image elements but also other processes such as a developing of a resist pattern and an etching and thus, only data concerning lithography is insufficient.
There is an experimental method as another example of the conventional OPC method. In this method, a gate pattern of a transistor constituting a memory cell is produced on, e.g., a wafer as an evaluation pattern, and the evaluation pattern is measured by, e.g., a scanning electron microscope, thereby correcting the pattern on the mask in accordance with data of the measurement. In this method, because a final size of the evaluation pattern which is actually produced is measured, it is possible to take into account elements concerning the proximity effect such as a mask, a lithography and an etching. However, such an evaluation pattern is only a portion of an actual semiconductor integrated circuit, and does not represent all of the patterns. Therefore, it is not easy to accurately correct, at high speed, a pattern of an actual semiconductor integrated circuit. As described above, it is difficult to accurately conduct the OPC at high speed in the conventional arts.